HEF4046BT Phase-Locked Loop (PLL) IC: Datasheet, Pinout, and Application Circuit Guide

The HEF4046BT is a monolithic integrated circuit from the venerable 4000 series CMOS family, representing one of the most versatile and widely used CMOS Phase-Locked Loop (PLL) ICs. Its primary function is to compare the phase of an input signal against a reference signal from a voltage-controlled oscillator (VCO) and adjust the VCO frequency until both signals are synchronized. This guide explores its datasheet, pin configuration, and a fundamental application circuit.

Datasheet Overview and Key Specifications

The HEF4046BT datasheet reveals a robust IC built on CMOS technology, ensuring low power consumption and a wide operating voltage range, typically from 3V to 15V. The device is notably resilient to noise and operates over a broad temperature range.

A defining feature of the HEF4046BT is its inclusion of two phase comparators (PC1 and PC2), offering flexibility for different application needs.

Phase Comparator 1 (PC1): An XOR gate that requires a 50% duty cycle on both input signals to achieve lock. It provides a wider capture range but can generate a ripple voltage on the output even when locked.

Phase Comparator 2 (PC2): An edge-triggered digital memory network. It is capable of locking onto signals with varying duty cycles and, crucially, provides lock-in detection capabilities, indicating when the PLL is synchronized.

The internal Voltage-Controlled Oscillator (VCO) generates an output signal whose frequency is directly proportional to the input voltage at the VCOin pin (pin 9). The frequency range is set by external resistors (R1, R2) and a capacitor (C1), allowing operation from a few hertz to several megahertz, depending on the supply voltage.

Other internal blocks include a source follower (pin 10) for buffering the demodulated input signal and a zener diode to stabilize the operating voltage for the VCO and the other comparators.

Pinout Configuration

Understanding the 16-pin DIP package pinout is critical for design:

Pin 1 (Phase Puls Out): Output of Phase Comparator 2.

Pin 2 (Phase Comp 1 Out): Output of Phase Comparator 1.

Pin 3 (Comp In): Input for the signal to be compared.

Pin 4 (VCO Out): The output of the internal Voltage-Controlled Oscillator.

Pin 5 (Inhibit): A high logic level on this pin disables the VCO and source follower to save power.

Pin 6 & Pin 7 (C1A & C1B): Pins for connecting the external VCO timing capacitor.

Pin 8 (GND): Ground reference.

Pin 9 (VCO In): The input for the control voltage that determines the VCO frequency.

Pin 10 (Demod Out): Buffered output of the demodulated input signal (source follower).

Pin 11 (R1): Pin for connecting an external resistor to set the VCO's maximum frequency.

Pin 12 (R2): Pin for connecting an external resistor to set the VCO's minimum frequency.

Pin 13 (Phase Comp 2 Out): Output of Phase Comparator 2.

Pin 14 (Sig In): The external input signal to which the PLL will lock.

Pin 15 (Zener): Connection to an internal zener diode cathode for regulated supply.

Pin 16 (VDD): Positive supply voltage.

Basic PLL Application Circuit

A fundamental application of the HEF4046BT is a frequency multiplier circuit. Here’s how to configure it:

1. External Components: Connect a capacitor (C1) between pins 6 and 7. Connect a resistor (R1) from pin 11 to ground. A second resistor (R2) between pin 12 and ground is optional for adjusting the minimum frequency.

2. Input Signal: Apply the input frequency signal (f_in) to pin 14.

3. Low-Pass Filter (LPF): This is the most critical external component. Connect a simple RC filter (a resistor and capacitor) between the phase comparator output (e.g., pin 2 or 13) and the VCO input (pin 9). This filter integrates the digital error pulses from the comparator into a smooth DC control voltage for the VCO. Its design dictates the loop dynamics, stability, and capture range.

4. Feedback: The VCO output (pin 4) is typically fed back to the comparator input (pin 3). To create a multiplier, a digital frequency divider (like a CD4017 or CD4040) is inserted in this feedback path. If a divide-by-N counter is used, the VCO will lock to a frequency that is N times the input frequency (f_out = N f_in).

This setup is the cornerstone for countless applications, including FM demodulation, tone decoding, frequency synthesis, and motor speed control.

ICGOODFIND: The HEF4046BT remains a cornerstone for analog and digital phase-locked loop designs due to its dual phase comparators, flexible VCO, and wide operating range. Its ability to be configured for both basic synchronization and complex frequency synthesis tasks makes it an indispensable tool for electronics engineers and hobbyists alike. While modern silicon PLLs offer higher frequency operation, the HEF4046BT's simplicity, robustness, and low-cost ensure its continued relevance in a vast array of electronic circuits.

Keywords: Phase-Locked Loop (PLL), Voltage-Controlled Oscillator (VCO), Phase Comparator, Low-Pass Filter (LPF), Frequency Synthesis